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AMD Athlon (Thunderbird) Whitepaper
Date: Sunday June 04, 2000
Category: Press Release
Manufacturer Link: AMD Discus -- BBS
The AMD Athlon (Thunderbird) whitepapers include in depth technical information on the new processor.
 
Processor Architecture Diagram and Summary


Superior Seventh-Generation AMD-K7 AMD Athlon Processor Architecture

 

AMD Athlon processors are based on a seventh-generation x86 microarchitecture that is technologically superior to previous sixth-generation architectures, such as the Pentium III and Pentium III Xeon processors. (See Table 1, Competitive Comparison, on previous page.) AMD Athlon processors feature a deeplysuper pipelined, nine-issue superscalar microarchitecture optimized for high clock frequency. AMD-K7AMD Athlon processors have a large dual-ported 128KB split-L1 cache (64KB instruction cache + 64KB data cache); a high-speed 256KB or 512KB L2 cache; a large multi-level, 512-entry Translation Look-aside Buffer (TLB); a two-way, 2048-entry branch prediction table; multiple parallel x86 instruction decoders; and multiple integer and floating point schedulers for independent superscalar, out-of-order, speculative execution of instructions. These elements are packed into an aggressive processing pipeline that includes 10-stage integer and 15-stage floating point pipelines.

The innovative AMD-K7AMD Athlon processor architecture implements the x86 instruction set by internally decoding x86 instructions into fixed-length "Macro-Ops" for higher instruction throughput and increased processing power. AMD-K7AMD Athlon processors contain nine execution pipelines-three for address calculations, three for integer calculations, and three for execution of FP/multimedia . MMXT instructions, 3DNow! technology, and x87 floating point instructions in the three /multimedia units, enabling enhanced performance with much of today's software.

Figure 1: AMD-K7T Processor Architecture Block Diagram 

 

AMD Athlon processors are fully binary-compatible with all existing x86 software and backward compatible with applications optimized for MMX and 3DNow! instructions. Using a data format and single instruction multiple data (SIMD) operations based on the MMX instruction model, AMD-K7AMD Athlon processors can produce as many as four, 32‑bit, single precision floating point results per clock cycle, potentially resulting in 4.0 Gflops at 1000 MHz (fully scalable). The Enhanced 3DNow! technology implemented in AMD-K7AMD Athlon processors include new integer multimedia instructions and and software-directed data movement instructions for optimizing such applications as digital content creation video and streaming video on the Internet streaming, as well as new instructions for DSP/communications applications.


AMD Athlon Processor Microarchitecture Summary:

 include:

 The industry's first nine-issue, superpipelined, superscalar x86 processor microarchitecture designed for high clock frequencies

· Multiple x86 instruction decoders

· Three out-of-order, superscalar, fully pipelined floating point execution units, which execute all x87 (floating point), MMX and 3DNow! instructions

· Three out-of-order, superscalar, pipelined integer units

· Three out-of-order, superscalar, pipelined address calculation units

· 72-entry instruction control unit

· Advanced dynamic branch prediction

Enhanced 3DNow! technology with new instructions to enable improved integer math calculations for speech or video encoding and improved data movement for Internet plug-ins and other streaming applications Three x86 instruction decoders issuing three x86 MacroOp instructions per cycle

 72-entry MacroOp Instruction control unit 

200MHz AMD Athlon processor system businterface (scalable beyond 400 MHz), enabling leading-edge maximum system bandwidth for data movement-intensive applications q High-performance cache architecture featuring a large split 128KB L1 cache, high-speed L2 cache of 256KB (full-speed, on-chip) or 512K (off-chip with support for up to 8MB), dedicated snoop tags, and a large multi-level, 512-entry Translation Look-aside Buffer

Previous Next

Page 1: AMD Athlon (Thunderbird) Whitepaper
Page 3: High Performance Cache Design
Page 4: 200MHz System Bus
Page 5: Application Optimizations and Infrastructure
Page 6: Summary and AMD Overview

More Press Releases-->

   11 / 17 / 2019 | 9:03PM
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